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<p>Creating course page via bot</p> <p><b>New page</b></p><div>{{Infobox Course<br /> | code = ELL830<br /> | name = Issues in Deep Submicron VLSI Design<br /> | credits = 3<br /> | credit_structure = 3-0-0<br /> | pre_requisites = <br /> | overlaps = <br /> }}<br /> <br /> == ELL830 : Issues in Deep Submicron VLSI Design ==<br /> VLSI Scaling rules and their impact: Short channel effect, Sub threshold leakage current, Gate leakage, VTH and body bias; Low power design: Technology level: 3D and 4 terminal MOSFETs, PDSOI, FDSOI, FINFET; Sub threshold leakage control: Transistor stacking in digital logic Multiple VTH, VDD designs, Dynamically adjustable VTH; Digital Circuit Design: Digital Sub-threshold Logic, Noise Immunity, Clock gating, Switching activity minimization; Analog Circuit Design: gm/ID Methodology for Design, Low power, low voltage opamp design, Subthreshold operation of opamps; Architecture level: Array Based Architectures, Parallel and Pipelined Architectures; Interconnects &amp; Noise: Capacitive &amp; Inductive coupling Analysis &amp; Optimization, Power/Ground Noise, L*di/dt noise, Power/Ground Placement Optimization, Decoupling.</div>

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