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	<id>https://wiki.devclub.in/index.php?action=history&amp;feed=atom&amp;title=COL215</id>
	<title>COL215 - Revision history</title>
	<link rel="self" type="application/atom+xml" href="https://wiki.devclub.in/index.php?action=history&amp;feed=atom&amp;title=COL215"/>
	<link rel="alternate" type="text/html" href="https://wiki.devclub.in/index.php?title=COL215&amp;action=history"/>
	<updated>2026-05-26T22:52:03Z</updated>
	<subtitle>Revision history for this page on the wiki</subtitle>
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	<entry>
		<id>https://wiki.devclub.in/index.php?title=COL215&amp;diff=2923&amp;oldid=prev</id>
		<title>DevanshKandpal: Bot: wrap bare course codes in wikilinks</title>
		<link rel="alternate" type="text/html" href="https://wiki.devclub.in/index.php?title=COL215&amp;diff=2923&amp;oldid=prev"/>
		<updated>2026-04-14T16:25:54Z</updated>

		<summary type="html">&lt;p&gt;Bot: wrap bare course codes in wikilinks&lt;/p&gt;
&lt;table style=&quot;background-color: #fff; color: #202122;&quot; data-mw=&quot;interface&quot;&gt;
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				&lt;td colspan=&quot;2&quot; style=&quot;background-color: #fff; color: #202122; text-align: center;&quot;&gt;← Older revision&lt;/td&gt;
				&lt;td colspan=&quot;2&quot; style=&quot;background-color: #fff; color: #202122; text-align: center;&quot;&gt;Revision as of 16:25, 14 April 2026&lt;/td&gt;
				&lt;/tr&gt;&lt;tr&gt;&lt;td colspan=&quot;2&quot; class=&quot;diff-lineno&quot; id=&quot;mw-diff-left-l4&quot;&gt;Line 4:&lt;/td&gt;
&lt;td colspan=&quot;2&quot; class=&quot;diff-lineno&quot;&gt;Line 4:&lt;/td&gt;&lt;/tr&gt;
&lt;tr&gt;&lt;td class=&quot;diff-marker&quot;&gt;&lt;/td&gt;&lt;td style=&quot;background-color: #f8f9fa; color: #202122; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #eaecf0; vertical-align: top; white-space: pre-wrap;&quot;&gt;&lt;div&gt;| credits = 5&lt;/div&gt;&lt;/td&gt;&lt;td class=&quot;diff-marker&quot;&gt;&lt;/td&gt;&lt;td style=&quot;background-color: #f8f9fa; color: #202122; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #eaecf0; vertical-align: top; white-space: pre-wrap;&quot;&gt;&lt;div&gt;| credits = 5&lt;/div&gt;&lt;/td&gt;&lt;/tr&gt;
&lt;tr&gt;&lt;td class=&quot;diff-marker&quot;&gt;&lt;/td&gt;&lt;td style=&quot;background-color: #f8f9fa; color: #202122; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #eaecf0; vertical-align: top; white-space: pre-wrap;&quot;&gt;&lt;div&gt;| credit_structure = 3-0-4&lt;/div&gt;&lt;/td&gt;&lt;td class=&quot;diff-marker&quot;&gt;&lt;/td&gt;&lt;td style=&quot;background-color: #f8f9fa; color: #202122; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #eaecf0; vertical-align: top; white-space: pre-wrap;&quot;&gt;&lt;div&gt;| credit_structure = 3-0-4&lt;/div&gt;&lt;/td&gt;&lt;/tr&gt;
&lt;tr&gt;&lt;td class=&quot;diff-marker&quot; data-marker=&quot;−&quot;&gt;&lt;/td&gt;&lt;td style=&quot;color: #202122; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #ffe49c; vertical-align: top; white-space: pre-wrap;&quot;&gt;&lt;div&gt;| pre_requisites = COL100, ELL101&lt;/div&gt;&lt;/td&gt;&lt;td class=&quot;diff-marker&quot; data-marker=&quot;+&quot;&gt;&lt;/td&gt;&lt;td style=&quot;color: #202122; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #a3d3ff; vertical-align: top; white-space: pre-wrap;&quot;&gt;&lt;div&gt;| pre_requisites = &lt;ins style=&quot;font-weight: bold; text-decoration: none;&quot;&gt;[[&lt;/ins&gt;COL100&lt;ins style=&quot;font-weight: bold; text-decoration: none;&quot;&gt;]]&lt;/ins&gt;, &lt;ins style=&quot;font-weight: bold; text-decoration: none;&quot;&gt;[[&lt;/ins&gt;ELL101&lt;ins style=&quot;font-weight: bold; text-decoration: none;&quot;&gt;]]&lt;/ins&gt;&lt;/div&gt;&lt;/td&gt;&lt;/tr&gt;
&lt;tr&gt;&lt;td class=&quot;diff-marker&quot; data-marker=&quot;−&quot;&gt;&lt;/td&gt;&lt;td style=&quot;color: #202122; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #ffe49c; vertical-align: top; white-space: pre-wrap;&quot;&gt;&lt;div&gt;| overlaps = ELL201&lt;/div&gt;&lt;/td&gt;&lt;td class=&quot;diff-marker&quot; data-marker=&quot;+&quot;&gt;&lt;/td&gt;&lt;td style=&quot;color: #202122; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #a3d3ff; vertical-align: top; white-space: pre-wrap;&quot;&gt;&lt;div&gt;| overlaps = &lt;ins style=&quot;font-weight: bold; text-decoration: none;&quot;&gt;[[&lt;/ins&gt;ELL201&lt;ins style=&quot;font-weight: bold; text-decoration: none;&quot;&gt;]]&lt;/ins&gt;&lt;/div&gt;&lt;/td&gt;&lt;/tr&gt;
&lt;tr&gt;&lt;td class=&quot;diff-marker&quot;&gt;&lt;/td&gt;&lt;td style=&quot;background-color: #f8f9fa; color: #202122; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #eaecf0; vertical-align: top; white-space: pre-wrap;&quot;&gt;&lt;div&gt;}}&lt;/div&gt;&lt;/td&gt;&lt;td class=&quot;diff-marker&quot;&gt;&lt;/td&gt;&lt;td style=&quot;background-color: #f8f9fa; color: #202122; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #eaecf0; vertical-align: top; white-space: pre-wrap;&quot;&gt;&lt;div&gt;}}&lt;/div&gt;&lt;/td&gt;&lt;/tr&gt;
&lt;tr&gt;&lt;td class=&quot;diff-marker&quot;&gt;&lt;/td&gt;&lt;td style=&quot;background-color: #f8f9fa; color: #202122; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #eaecf0; vertical-align: top; white-space: pre-wrap;&quot;&gt;&lt;br&gt;&lt;/td&gt;&lt;td class=&quot;diff-marker&quot;&gt;&lt;/td&gt;&lt;td style=&quot;background-color: #f8f9fa; color: #202122; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #eaecf0; vertical-align: top; white-space: pre-wrap;&quot;&gt;&lt;br&gt;&lt;/td&gt;&lt;/tr&gt;
&lt;tr&gt;&lt;td class=&quot;diff-marker&quot;&gt;&lt;/td&gt;&lt;td style=&quot;background-color: #f8f9fa; color: #202122; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #eaecf0; vertical-align: top; white-space: pre-wrap;&quot;&gt;&lt;div&gt;== COL215 : Digital Logic &amp;amp; System Design ==&lt;/div&gt;&lt;/td&gt;&lt;td class=&quot;diff-marker&quot;&gt;&lt;/td&gt;&lt;td style=&quot;background-color: #f8f9fa; color: #202122; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #eaecf0; vertical-align: top; white-space: pre-wrap;&quot;&gt;&lt;div&gt;== COL215 : Digital Logic &amp;amp; System Design ==&lt;/div&gt;&lt;/td&gt;&lt;/tr&gt;
&lt;tr&gt;&lt;td class=&quot;diff-marker&quot;&gt;&lt;/td&gt;&lt;td style=&quot;background-color: #f8f9fa; color: #202122; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #eaecf0; vertical-align: top; white-space: pre-wrap;&quot;&gt;&lt;div&gt;The course contents can be broadly divided into two parts. First part deals with the basics of circuit design and includes topics like circuit minimization, sequential circuit design and design of and using RTL building blocks. The second part is focused on ASIC style system design and introduces VHDL, FPGA as implementation technology, synthesis steps as well as testing techniques. Course ends with introducing the challenges of embedded design where software is becoming integral to all devices. The laboratory assignments are a key component of this course and requires students to design and implement circuits and sub-systems on FPGA kits covering almost all the topics covered in the lectures.&lt;/div&gt;&lt;/td&gt;&lt;td class=&quot;diff-marker&quot;&gt;&lt;/td&gt;&lt;td style=&quot;background-color: #f8f9fa; color: #202122; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #eaecf0; vertical-align: top; white-space: pre-wrap;&quot;&gt;&lt;div&gt;The course contents can be broadly divided into two parts. First part deals with the basics of circuit design and includes topics like circuit minimization, sequential circuit design and design of and using RTL building blocks. The second part is focused on ASIC style system design and introduces VHDL, FPGA as implementation technology, synthesis steps as well as testing techniques. Course ends with introducing the challenges of embedded design where software is becoming integral to all devices. The laboratory assignments are a key component of this course and requires students to design and implement circuits and sub-systems on FPGA kits covering almost all the topics covered in the lectures.&lt;/div&gt;&lt;/td&gt;&lt;/tr&gt;
&lt;/table&gt;</summary>
		<author><name>DevanshKandpal</name></author>
	</entry>
	<entry>
		<id>https://wiki.devclub.in/index.php?title=COL215&amp;diff=550&amp;oldid=prev</id>
		<title>Prashantt492: Creating course page via bot</title>
		<link rel="alternate" type="text/html" href="https://wiki.devclub.in/index.php?title=COL215&amp;diff=550&amp;oldid=prev"/>
		<updated>2026-03-04T09:59:38Z</updated>

		<summary type="html">&lt;p&gt;Creating course page via bot&lt;/p&gt;
&lt;p&gt;&lt;b&gt;New page&lt;/b&gt;&lt;/p&gt;&lt;div&gt;{{Infobox Course&lt;br /&gt;
| code = COL215&lt;br /&gt;
| name = Digital Logic &amp;amp; System Design&lt;br /&gt;
| credits = 5&lt;br /&gt;
| credit_structure = 3-0-4&lt;br /&gt;
| pre_requisites = COL100, ELL101&lt;br /&gt;
| overlaps = ELL201&lt;br /&gt;
}}&lt;br /&gt;
&lt;br /&gt;
== COL215 : Digital Logic &amp;amp; System Design ==&lt;br /&gt;
The course contents can be broadly divided into two parts. First part deals with the basics of circuit design and includes topics like circuit minimization, sequential circuit design and design of and using RTL building blocks. The second part is focused on ASIC style system design and introduces VHDL, FPGA as implementation technology, synthesis steps as well as testing techniques. Course ends with introducing the challenges of embedded design where software is becoming integral to all devices. The laboratory assignments are a key component of this course and requires students to design and implement circuits and sub-systems on FPGA kits covering almost all the topics covered in the lectures.&lt;/div&gt;</summary>
		<author><name>Prashantt492</name></author>
	</entry>
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